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M48Z512A M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER(R) SRAM
Features

Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Automatic power-fail chip deselect and WRITE protection Two WRITE protect voltages: (VPFD = power-fail deselect voltage) - M48Z512A: VCC = 4.75 to 5.5 V, 4.5 V VPFD 4.75 V - M48Z512AY: VCC = 4.5 to 5.5 V, 4.2 V VPFD 4.5 V - M48Z512AV: VCC = 3.0 to 3.6 V, 2.8 V VPFD 3.0 V M48Z512AV not for new design (see M48Z512BV). Contact ST sales office for availability. Battery internally isolated until power is applied Pin and function compatible with JEDEC standard 512 K x 8 SRAMs PMDIP32 is an ECOPACK(R) package RoHS compliant - Lead-free second level interconnect
32 1
PMDIP32 module (PM)
Description
The M48Z512A/Y/V ZEROPOWER(R) RAM is a non-volatile, 4,194,304-bit static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP Module.

August 2010
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www.st.com 1
Contents
M48Z512A, M48Z512AY, M48Z512AV
Contents
1 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PMDIP32 - 32-pin plastic DIP module, package mechanical data. . . . . . . . . . . . . . . . . . . 17 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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List of figures
M48Z512A, M48Z512AY, M48Z512AV
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 - 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Device overview
1
Device overview
Figure 1. Logic diagram
VCC
19 A0-A18 M48Z512A M48Z512AY M48Z512AV
8 DQ0-DQ7
W E G
VSS
AI02043
Table 1.
Signal names
A0-A18 DQ0-DQ7 E G W VCC VSS Address inputs Data inputs/outputs Chip enable input Output enable input WRITE enable input Supply voltage Ground
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Device overview Figure 2. DIP connections
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z512A 8 M48Z512AY 9 M48Z512AV 10 11 12 13 14 15 16
M48Z512A, M48Z512AY, M48Z512AV
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI02044
Figure 3.
Block diagram
VCC
A0-A18
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
512K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI02045
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Operating modes
2
Operating modes
The M48Z512A/Y/V also has its own power-fail detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. The ZEROPOWER(R) RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect
Operating modes
VCC 4.75 to 5.5 V or 4.5 to 5.5 V or 3.0 to 3.6 V VSO to VPFD (min)(1) E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery backup mode
VSO(1)
1. X = VIH or VIL; VSO = battery backup switchover voltage.
Note:
See Table 10 on page 16 for details.
2.1
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The device architecture allows ripple-through access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E (chip enable) and G (output enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of chip enable access time (tELQV) or output enable access Time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain low, output data will remain valid for output data hold time (tAXQX) but will go indeterminate until the next address access.
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Operating modes Figure 4.
M48Z512A, M48Z512AY, M48Z512AV Chip enable or output enable controlled, READ mode AC waveforms
tAVAV
A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7
VALID tAXQX tEHQZ
tGHQZ
DATA OUT
AI01221
1. WRITE enable (W) = high
Figure 5.
Address controlled, READ mode AC waveforms
A0-A18 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI01220
tAXQX
1. Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
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M48Z512A, M48Z512AY, M48Z512AV Table 3.
Symbol
Operating modes
READ mode AC characteristics
Parameter
(1)
M48Z512A/Y -70 Min Max
M48Z512A/Y/V -85 Min 85 Max
Unit
tAVAV tAVQV tELQV tGLQV tELQX
(2)
READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z
70 70 70 35 5 5 30 20 5
ns 85 85 45 ns ns ns ns ns 35 25 ns ns ns
5 5
tGLQX(2) tEHQZ(2)
tGHQZ(2) Output enable high to output Hi-Z tAXQX Address transition to output transition
5
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF.
2.2
WRITE mode
The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
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Operating modes Figure 6.
M48Z512A, M48Z512AY, M48Z512AV WRITE enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID tAVWH tAVEL tWHAX
E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01222
tWHQX
1. Output enable (G) = high.
Figure 7.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A18
VALID tAVEH tAVEL tELEH tEHAX
E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
1. Output enable (G) = high.
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M48Z512A, M48Z512AY, M48Z512AV Table 4.
Symbol
Operating modes
WRITE mode AC characteristics
Parameter
(1)
M48Z512A/Y -70 Min Max
M48Z512A/Y/V -85 Min 85 0 0 65 75 5 15 35 35 0 10 Max
Unit
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3)
WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition
70 0 0 55 55 5 15 30 30 0 10 25 65 65 5
ns ns ns ns ns ns ns ns ns ns ns 30 ns ns ns ns
75 75 5
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. CL = 5 pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, WRITE protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the application note AN1012.
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Operating modes
M48Z512A, M48Z512AY, M48Z512AV
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (see Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount). Figure 8. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
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Maximum ratings
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol TA TSTG TBIAS TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Grade 1 Ambient operating temperature Grade 6 Storage temperature (VCC off) Grade 1 Temperature under bias Grade 6 Lead solder temperature for 10 seconds Input or output voltages M48Z512A/512AY Supply voltage M48Z512AV Output current Power dissipation -0.3 to 4.6 20 1 V mA W -40 to 85 260 -0.3 to 7 -0.3 to 7.0 C V V -40 to 85 -40 to 85 0 to 70 C C Value 0 to 70 C Unit
1. Soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. In order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 C. Furthermore, the devices shall not be exposed to IR reflow.
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode.
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DC and AC parameters
M48Z512A, M48Z512AY, M48Z512AV
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Grade 1 Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages Grade 6 M48Z512A/512AY 4.75 to 5.5 V or 4.5 to 5.5 0 to 70 -40 to 85 100 5 0 to 3 1.5 M48Z512AV Unit 3.0 to 3.6 0 to 70 C -40 to 85 50 5 0 to 3 1.5 pF ns V V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC measurement load circuit
DEVICE UNDER TEST 650
CL = 100 pF (1) or 30 pF
1.75V
CL includes JIG capacitance
AI03903
1. Excluding open drain output pins; 50 pF for M48Z512AV.
Table 7.
Symbol CIN CIO(3)
Capacitance
Parameter(1)(2) Input capacitance Input/output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V (M48Z512A/Y) or 3.3 V (M48Z512AV); sampled only, not 100% tested. 2. Outputs deselected. 3. At 25 C.
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M48Z512A, M48Z512AY, M48Z512AV Table 8.
Sym
DC and AC parameters
DC characteristics
Test condition(1) Parameter M48Z512A/Y -70 Min Max 1 1 115 10 5 -0.3 2.2 IOL = 2.1 mA IOH = -1 mA 2.4 0.8 VCC + 0.3 0.4 2.2 -0.3 2.2 M48Z512AV -85 Min Max 1 1 50 4 3 0.6 VCC + 0.3 0.4 A A mA mA mA V V V V Unit
ILI(2) ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH
Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage
0 V VIN VCC 0 V VOUT VCC E = VIL outputs open E = VIH E VCC - 0.2 V
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. Outputs deselected.
Figure 10. Power down/up mode AC waveforms
tF
VCC VPFD (max) VPFD (min) VSO VSS
tWP tFB
tDR tRB DON'T CARE
tR tER
RECOGNIZED
INPUTS
(Including E)
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI02385
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DC and AC parameters Table 9.
Symbol tF(2) tFB(3) tR tRB tWPT tER
M48Z512A, M48Z512AY, M48Z512AV Power down/up AC characteristics
Parameter(1) Min 300 M48Z512A/Y 10 s M48Z512AV 150 10 1 M48Z512A/Y 40 40 40 150 s M48Z512AV 250 120 ms s s Max Unit s
VPFD (max) to VPFD (min) VCC fall time VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time WRITE protect time E recovery time
1. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/WRITE protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Symbol
Power down/up trip points DC characteristics
Parameter(1)(2) M48Z512A Min 4.5 4.2 2.8 Typ 4.6 4.3 2.9 3.0 2.5 10 Max 4.75 4.5 3.0 Unit V V V V V Years
VPFD
Power-fail deselect voltage
M48Z512AY M48Z512AV M48Z512A/Y
VSO tDR
(3)
Battery backup switchover voltage M48Z512AV Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 C or -40 to 85 C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V, or 3.0 to 3.6 V (except where noted). 3. At 25 C; VCC = 0 V.
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Package mechanical data
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 11. PMDIP32 - 32-pin plastic DIP module, package outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
1. Drawing is not to scale.
Table 11.
Symb
PMDIP32 - 32-pin plastic DIP module, package mechanical data
mm Typ Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 38.10 14.99 3.05 1.91 32 16.00 3.81 2.79 0.59 0.33 43.18 18.80 2.79 1.50 0.590 0.120 0.075 32 0.630 0.150 0.110 Max 9.52 Typ inches Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 0.023 0.013 1.700 0.740 0.110 Max 0.375
A A1 B C D E e1 e3 eA L S N
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Part numbering
M48Z512A, M48Z512AY, M48Z512AV
6
Part numbering
Table 12.
Example:
Ordering information scheme
M48Z 512AY -70 PM 1
Device type M48Z
Supply voltage and WRITE protect voltage 512A = VCC = 4.75 to 5.5 V; VPFD = 4.5 to 4.75 V 512AY = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 512AV(1) = VCC = 3.0 to 3.6 V; VPFD = 2.8 to 3.0 V
Speed -70 = 70 ns (for M48Z512A/Y) -85 = 85 ns (for M48Z512A/Y/V)
Package PM = PMDIP32
Temperature range 1 = 0 to 70 C 6 = -40 to 85 C
1. M48Z512AV not for new design (see M48Z512BV). Contact ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Environmental information
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
M48Z512A, M48Z512AY, M48Z512AV
8
Revision history
Table 13.
Date Mar-2000 19-Jul-2000 15-Jan-2001 19-Dec-2001 08-Feb-2002 29-May-2002 18-Nov-2002 17-Sep-2003 30-Nov-2004 21-Dec-2004 22-Feb-2005
Revision history
Revision 1 1.1 1.2 2 2.1 2.2 2.3 2.4 3 4 5 First issue M48Z12AV added Changed LPSRAM device (Table 2) Reformatted; added temperature information (Table 3, Table 4, Table 7, Table 8, Table 9, and Table 10); remove chipset option from Ordering Information (Table 12); remove reference to "clock" Remove 85ns speed grade (Table 3, Table 4, and Table 8) Modify reflow time and temperature footnotes (Table 5) Modified SMT text (Figure 1, Figure , and Table 2) Remove references to M68xxx (obsolete) part (Figure and Table 2); update disclaimer Reformatted; remove extended temperature references (Table 12) Update Marketing Status for qualification, correct drawing (Figure and Table 12) IR reflow, SO package updates (Table 5) Document reformatted. ECOPACK package text added on coverpage. Note 2 concerning Leaded SOIC package removed below Table 5. Updated PMDIP32 package mechanical data in Section 5: Package mechanical data; updated TA to include Grade 1 (0 to 70C) and Grade 6 (-40 to 85C). Indicated that M48Z512AV is Not for New Design; removed all SNAPHAT(R) battery and SOIC package references; updated Section 5: Package mechanical data. Updated Features, Section 3, Table 12, ECOPACK(R) text in Section 5; added Section 7: Environmental information. Changes
21-Dec-2006
6
7-Nov-2008
7
02-Aug-2010
8
20/21
Doc ID 5146 Rev 8
M48Z512A, M48Z512AY, M48Z512AV
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Doc ID 5146 Rev 8
21/21

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